module i2s_recieve_top(
    input   wire    i_clk_50m,      //主时钟输入，连接至片上晶振（50MHz）
    input   wire    i_rst_n,        //复位信号输入
    //i2s物理接口
    input   wire    i_i2s_sdata,    //串行数据输入
    output  wire    o_i2s_mclk,     //主时钟输出
    output  wire    o_i2s_bclk,     //bitclock输出
    output  wire    o_i2s_lrclk,    //lrclock输出
    //数据输出（连接至下一模块）
    output  wire    [23:0]  o_i2s_rxdata_l,     //
    output  wire    [23:0]  o_i2s_rxdata_r,     //
    output  wire    o_i2s_rxdata_vld_l,
	output  wire    o_i2s_rxdata_vld_r
);

	/*内部连线*/
	assign o_i2s_mclk = i_clk_50m;
	
	/*模块连接*/
	//必要的端口总线定义
	wire	o_i2s_bclk_inst;
	assign	o_i2s_bclk = o_i2s_bclk_inst;
	
	wire	o_i2s_lrclk_inst;
	assign	o_i2s_lrclk = o_i2s_lrclk_inst;
	
	wire	i_rst_n_inst;
	assign	i_rst_n_inst = i_rst_n;
	
	//i2s_clk_gen模块
	i2s_clk_gen #(
		.BIT	(32)
	)ur_i2s_clk_gen(
    .clk_50m	(i_clk_50m),
    .rst_n		(i_rst_n_inst),
    .bclk		(o_i2s_bclk_inst),
    .lrclk		(o_i2s_lrclk_inst)
	);
	
	//i2s_reciever模块
    
    
	i2s_reciever u_i2s_reciever(
    .bclk		(o_i2s_bclk_inst),	//bit clock
    .lrclk		(o_i2s_lrclk_inst),	//lrclock
	.sdata		(i_i2s_sdata),	//data in
	.rst_n		(i_rst_n_inst),	//reset signal
	
	.ldata		(o_i2s_rxdata_l),	//
	.rdata		(o_i2s_rxdata_r),	//
	.ldata_vld	(o_i2s_rxdata_vld_l),
	.rdata_vld	(o_i2s_rxdata_vld_r)
	);
	
endmodule